1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling the same, and particularly to a semiconductor memory device including so-called replica cells and a method of controlling the same.
2. Description of the Related Art
General semiconductor memory devices execute reading of data by means of a sense amplifier circuit, which senses at a certain timing a signal level that appears on a bit line in accordance with the data retained in a memory cell, and amplifies the signal level. Accordingly, in order to accelerate the operation speed of a semiconductor memory device, it is desirable to shorten the time taken from selection of a memory cell to activation of the sense amplifier.
However, if the sense amplifier circuit is activated too early, the sensing/amplifying operation of the sense amplifier circuit is started before a sufficient signal level appears on a bit line, which increases the possibility of erroneous reading. Hence, it is necessary to set an optimum timing at which no erroneous reading occurs and at which it is possible to accelerate the operation speed.
Here, as a technique for generating (rising up) an activation signal for the sense amplifier at an appropriate timing, a semiconductor memory device is known which utilizes a replica circuit (see, e.g., JPH9-259589A). The replica circuit includes replica cells configured in a structure that is the same as or similar to a memory cell array. The replica circuit generates (simulates), based on the replica cells, a timing signal for reading of data from the memory cells, and activates the sense amplifier based on this timing signal. The replica circuit is configured as an arrangement of a plurality of replica cells having a structure that is the same as or similar to the memory cells.
Incidentally, along with increasing miniaturization of the memory cells, supply voltage of semiconductor memory devices has become lower. Due to this, there has been found a more noticeable dispersion in the amount of delay of output signals output by the respective memory cells. However, existing replica circuits are not designed in consideration of such dispersion, and suffer from a problem of high possibility of erroneous reading due to the dispersion.